In the existing uninterruptible power supply, the main circuit topology thereof is shown in FIG. 1. As shown in FIG. 1, an inductance L1, a first switching transistor Q1, a second switching transistor Q2, a body diode of a third switching transistor Q3, and a body diode of a fourth switching transistor Q4 constitute a power factor correction (PFC) circuit. The third switching transistor Q3, the fourth switching transistor Q4, a fifth switching transistor Q5, a sixth switching transistor Q6, an inductance L2, and a capacitance C2 constitute a full-bridge inverter circuit. After power factor correction by the PFC circuit, the input current becomes a sine wave in phase with the mains power supply and has low harmonic content. The full-bridge inverter circuit then provides the load a high-quality sine voltage inverted from the DC voltage, which is outputted by the PFC circuit.
To analyze the structure of the circuit, the bridge arm consisting of the first switching transistor Q1 and the second switching transistor Q2 is referred to as a rectifying bridge arm. The bridge arm consisting of the third switching transistor Q3 and the fourth switching transistor Q4 is referred to as a midline bridge arm, and the bridge arm consisting of the fifth switching transistor Q5 and the sixth switching transistor Q6 is referred to an inverter bridge arm. The midline bridge arm consisting of the third switching transistor Q3 and the fourth switching transistor Q4 is shared by the PFC circuit and a full-bridge inverter circuit. Therefore, the first advantage of this circuit topology is less switching transistors and lower circuit cost. Since the PFC circuit sharing the midline bridge arm with the full-bridge inverter circuit, and the rectified current of the PFC circuit and the inverted current of the inverter circuit passing through the switching transistors of the midline bridge arm (Q3 or Q4) are in opposite directions to each other in most of cases, which may be counteracted mostly, the current passing through the third switching transistor Q3 and the fourth switching transistor Q4 is small. Thus the power consumption thereon is small as well. Therefore, the second advantage of this circuit topology is the high operating efficiency of the UPS circuitry.
Since there is a shared midline bridge arm, the operation of the PFC circuit and that of the inverter circuit have to operate synchronously. Otherwise, the circuit cannot operate normally. However, due to different zero-crossing switching modes of the PFC circuit and the inverter circuit or the errors in phase-locking and in the controlled quantity, there will be error of zero-crossing synchronization between the PFC circuit and the inverter circuit. It is always the cases that the PFC circuit zero-crossing leads the inverter circuit with one or even several switching cycles, or the inverter circuit zero-crossing leads the PFC circuit with one or even several switching cycles. If only considering zero-crossing synchronization of the midline bridge arm and the PFC circuit regardless of the zero-crossing of the inverter circuit, or only considering zero-crossing synchronization of the midline bridge arm and the inverter circuit regardless of the zero-crossing of the PFC circuit during the zero-crossing switching, the output voltage or the input current of the UPS would oscillate, which then influences the performance indices of the UPS, such as, the Total Harmonic Distortion of Voltage (THDv) of the output voltage and the Total Harmonic Distortion of Current (THDi) of the input current.